Engineering Academy takes on RISC-V in next installment of educational event


The open source RISC-V Instruction Set Architecture (ISA) has taken the developer community by storm as more and more companies have implemented RISC-V based chips. The architecture empowers a generation of developers by giving everyone, regardless of size, the ability to compete. It has also fostered a level of customization that is driving innovations in areas ranging from microcontrollers to artificial intelligence.

As part of the new Engineering Academy educational platform, an event on September 8 on Extend the RISC-V ecosystem of our colleagues from Electronic design will dive into RISC-V from several angles. Each session, led by industry leaders and subject matter experts, will cover topics ranging from chip design and architecture to software development.

The incredible panel of experts will discuss how the open-source RISC-V architecture will enable chip design and how it can promote industry-wide collaboration to create solutions based on a common set of standards and specifications. Panelists include:

  • Calista Redmond, CEO, RISC-V International
  • Dirk Akemann, Marketing Manager, SEGGER
  • Drew Barbier, Senior Director of Product Management, SiFive
  • Rupert Baines, CMO, Codasip

Technical sessions will include:

RISC-V Architecture Considerations

The adoption of RISC-V and the expansion of accessible markets are directly related to the extent to which the design ecosystem and infrastructure have been developed. We talk to Jeff Hancock of Siemens Embedded about the development progress of this ecosystem.

RISC-V from a chip perspective

RISC-V promises a lot of things, but you still have to be able to build a chip with it. In this technical session, we talk about the RISC-V ecosystem from the perspective of IP cores and ISAs. Drew Barbier Sr., SiFive’s Director of Product Management, will shed light on this topic.

Reference models for RISC-V processor verification and software development

RISC-V’s open ISA standard provides new degrees of design freedom for system designers, software developers, and processor hardware implementers. The ISA specification is supported by the growing ecosystem of partners who provide the essential infrastructure that developers can rely on from project inception through production. Imperas’ Simon Davidmann will cover adaptable verification methods that complement RISC-V design innovations, as well as the use of virtual platforms for software development and architectural exploration with RISC-V custom instructions.

Registration is free and prizes can be won by active session visitors who accumulate the most points.


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